Power-converter control apparatus employing pulse width modulation and adjusting duration of a zero-voltage vector

ABSTRACT

An apparatus for controlling a power converter including a voltage-vector control unit that determines, based on voltage instruction value for the power converter, a voltage vector output from a power converter in one control cycle of pulse width modulation control and times for outputting of the voltage vector, a voltage-vector adjusting unit that adjusts the time of outputting of the voltage vector so that time of outputting of a zero-voltage vector is larger than a fixed time or zero, and a firing-pulse generating unit that generates a signal for turning on and off a semiconductor switching element included in the power converter, based on the time of outputting of the voltage vector adjusted by the voltage-vector adjusting unit.

TECHNICAL FIELD

The present invention relates to a power-converter control apparatusdriven by pulse width modulation (PWM) control and, particularly, acontrolling device that suppresses an abnormally high voltage(hereinafter, “surge voltage”) occurring at a cable-connection end of aload when a connection cable between the power converter and the load islong.

BACKGROUND ART

FIG. 1 is a drawing for explaining a connection cable between aninverter, which is a power converter driven by PWM control, and a motor.In FIG. 1, an inverter 1, which is a power converter, has connectedthereto a motor 2 via a cable 3. In the inverter 1, a switchingoperation of semiconductor switching elements (for example, IGBTelements) is controlled through PWM control by a controlling unit notshown to generate three-phase voltages (uvw) varying stepwise from adirect-current power supply having a voltage Vdc, and these voltages areoutput to the motor 2 via the connection cable 3.

Here, when this connection cable 3 between the inverter 1 and the motor2 is long, a surge voltage exceeding twice a direct-current bus voltageVdc may occur at cable-connection ends of the motor 2. That is, theconnection cable 3 can be considered as a resonant circuit composed of awiring inductance and a floating capacitance. When the connection cable3 is long, the wiring inductance and the floating inductance are bothincreased, thereby reducing a resonant frequency of the resonantcircuit. As a result, before resonance excited at the resonant circuitdue to a stepwise change in voltage produced by the inverter 1 isattenuated, the next stepwise change in voltage is applied. Suchrepeated application increases resonance, thereby causing a surgevoltage, which is a voltage higher than usual, at the cable connectionends of the motor 2.

With reference to FIGS. 2A and 3B, details of the surge voltageoccurring at the cable connection ends of the motor 2 are described.FIGS. 2A and 3B are drawings that depict line-to-line voltage waveformsat both ends of the connection cable 3 shown in FIG. 1.

FIG. 2A depicts a case where an inverter-end line-to-line voltageVuv_inv is varied stepwise as Vdc→0→Vdc. At this time, when a pulsewidth in voltage change coincides with half of a resonant cycle, asshown in FIG. 2B, a motor-end line-to-line voltage Vuv_motor becomesthree times as high as the direct-current bus voltage Vdc at maximum.

Also, FIG. 3A depicts a case where the inverter-end line-to-line voltageVuv_inv is varied stepwise as 0→Vdc→−Vdc→0. At this time, as shown inFIG. 3B, the motor-end line-to-line voltage Vuv_motor becomes four timesas high as the direct-current bus voltage Vdc at maximum.

From the description with reference to FIGS. 2A and 3B, it is known thatif the pulse width in voltage change is sufficiently large, afterresonance occurring due to a stepwise voltage change is attenuated, thenext stepwise voltage change is applied, and therefore a surge voltageexceeding twice the direct-current bus voltage Vdc does not occur.

To solve this surge-voltage problem, for example, first and secondpatent documents disclose a technology of monitoring a firing pulsewidth of each of IGBT elements, which serves as a line-to-line voltagepulse width of the inverter and limiting a maximum value of the firingpulse width to be equal to or smaller than a predetermined value and aminimum value of the firing pulse width to be equal to or larger than apredetermined value. The first patent document: U.S. Pat. No. 5,671,130;and the second patent document: U.S. Pat. No. 5,990,658.

Also, for example, third and fourth patent documents disclose atechnology of monitoring each phase-voltage instruction value input tothe PWM controller and limiting a maximum value of each phase-voltageinstruction value to be equal to or smaller than a predetermined valueand a minimum value of each phase voltage to be equal to or larger thana predetermined value. The third patent document: U.S. Pat. No.5,912,813; and the fourth patent document: U.S. Pat. No. 6,014,497.

However, the firing pulse width or the voltage instruction value variesfor each phase. Therefore, the firing pulse width or the voltageinstruction value is required to be limited individually for each phase.That is, to suppress a surge voltage exceeding twice the direct-currentbus voltage Vdc by applying the technologies disclosed in the patentdocuments, if the firing pulse width of each IGBT element or the maximumand minimum values of each phase-voltage instruction value are limited,a plurality of controlling units that control the maximum and minimumvalues of each phase are required.

Also, one problem of this configuration is that, when the firing pulsewidth or the voltage instruction value of one phase is limited, aninfluence on other phases cannot be considered. Moreover, in relation tothis problem, there is another problem in which all phases cannot becollectively handled for optimal limitation.

The present invention is devised in view of the above, and an object ofthe present invention is to provide a power-converter control apparatus,the device being capable of collectively handling all phases andoptimally suppressing a surge voltage exceeding twice a direct-currentbus voltage.

DISCLOSURE OF THE INVENTION

It is an object of the present invention to solve at least the aboveproblems in the conventional technology. An apparatus for controlling apower converter according to one aspect of the present inventionincludes a voltage-vector control unit that determines, based on avoltage instruction value for the power converter, a voltage vectoroutput from the power converter in one control cycle of the pulsewidth-modulation control and time of outputting of the voltage vector; avoltage-vector adjusting unit that adjusts the time of outputting of thevoltage vector in such a manner that the time of outputting of azero-voltage vector is longer than a fixed time or zero; and afiring-pulse generating unit that generates a signal for turning on andoff a semiconductor switching element included in the power converter,based on the time of outputting of the voltage vector as adjusted by thevoltage-vector adjusting unit.

Other objects, features, and advantages of the present invention willbecome apparent from the following detailed description of the inventionwhen read in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a drawing for explaining a connection cable between aninverter, which is a power converter driven by PWM control, and a motor;

FIGS. 2A and 2B are (first) drawings that illustrate line-to-linevoltage waveforms between both ends of the connection cable shown inFIG. 1;

FIGS. 3A and 3B are (second) drawings that illustrate line-to-linevoltage waveforms between both the ends of the connection cable shown inFIG. 1;

FIG. 4 is a block diagram depicting the structure of a power-convertercontrol apparatus according to a first embodiment of the presentinvention;

FIG. 5 is a circuit diagram depicting a basic structure of a three-phasevoltage inverter for use in the embodiment as the power converter drivenby PWM control;

FIG. 6 is a drawing for explaining a relation between turned-on IGBTelements and voltage vectors in eight control states of the invertershown in FIG. 5;

FIG. 7 is a drawing for explaining voltage vectors;

FIG. 8 is a drawing for explaining a relation between phases and voltagevectors;

FIG. 9 is a flowchart for explaining the operation of a voltage-vectoradjusting unit shown in FIG. 4;

FIGS. 10A, 10B, and 10C are diagrams for explaining loci of magneticflux vectors when the voltage vectors are adjusted;

FIG. 11 is a time chart for explaining the operation of a fifing-pulsegenerating unit shown in FIG. 4;

FIGS. l2A to 12D are drawings for explaining a relation between theprogression of the voltage vectors and line-to-line voltages;

FIG. 13 is a drawing that depicts line-to-line voltage patternsextracted in view of a pulse polarity, an output time of zero-voltagevectors, and an output time of voltage vectors other than thezero-voltage vectors;

FIGS. 14A to 14H are drawings for explaining surge voltages occurringdue to the line-to-line voltages shown in FIG. 13;

FIG. 15 is a flowchart for explaining the operation of a voltage-vectoradjusting unit included in a controlling device for the power controlleraccording to a second embodiment of the present invention;

FIG. 16 is a block diagram depicting the structure of a power-convertercontrol apparatus according to a third embodiment of the presentinvention;

FIG. 17 is a flowchart showing a voltage-vector adjusting unit shown inFIG. 16;

FIG. 18 is a flowchart for explaining the operation of a voltage-vectoradjusting unit included in a power-converter control apparatus accordingto a fourth embodiment of the present invention;

FIG. 19 is a block diagram showing a power-converter control apparatusaccording to a fifth embodiment of the present invention;

FIG. 20 is a flowchart for explaining the operation of a voltage-vectoradjusting unit shown in FIG. 19;

FIG. 21 is a flowchart for explaining the operation of a voltage-vectoradjusting unit included in a power-converter control apparatus accordingto a sixth embodiment of the present invention;

FIG. 22 is a block diagram depicting the structure of a power-convertercontrol apparatus according to a seventh embodiment of the presentinvention;

FIG. 23 is a flowchart for explaining the operation of a voltage-vectoradjusting unit shown in FIG. 22;

FIGS. 24A to 24C are drawings for explaining an error-calculatingoperation to be performed by the voltage-vector adjusting unit shown inFIG. 22;

FIG. 25 is a flowchart for explaining the operation of a voltage-vectoradjusting unit included in a power-converter control apparatus accordingto an eighth embodiment of the present invention; and

FIG. 26 is a flowchart for explaining the operation of a voltage-vectoradjusting unit included in a power-converter control apparatus accordingto a ninth embodiment of the present invention

BEST MODE FOR CARRYING OUT THE INVENTION

Exemplary embodiments of a power-converter control apparatus accordingto the present invention are described below in detail with reference tothe accompanying drawings.

FIG. 4 is a block diagram depicting the structure of a power-convertercontrol apparatus according to a first embodiment of the presentinvention. A controlling device shown in FIG. 4 includes avoltage-vector control unit 11, a voltage-vector adjusting unit 12, anda firing-pulse generating unit 13.

The voltage-vector control unit 11 selects, from out of voltageinstruction values Vu, Vv, and Vw of the respective phases of a powerconverter, voltage vectors to be output from the power converter withinone control cycle of PWM control (in an example shown in the drawing,V0, V1, V2, and V7), and calculates their output times (t0, t1, t2, t7).

The voltage-vector adjusting unit 12 outputs the voltage vectors inputfrom the voltage-vector control unit 11 (in the example show in thedrawing, V0, V1, V2, V7) as they are, and also adjusts the output times(t0, t1, t2, t7) of these voltage vectors so that a zero-voltage-vectoroutput time is equal to or larger than a predetermined value for output(t0′, t1′, t2′, t7′).

The firing-pulse generating unit 13 generates, based on the voltagevectors input from the voltage-vector adjusting unit 12 and thevoltage-vector output times adjusted at the voltage-vector adjustingunit 12, on-off signals “PQ1, PQ2, PQ3, PQ4, PQ5, PQ6, and PQ7” forsemiconductor switching elements that form the power converter.

A specific operation of each block is described below. First, withreference to FIGS. 5 to 8, the operation of the voltage-vector controlunit 11 is described. Here, FIG. 5 is a circuit diagram showing a basicstructure of a three-phase voltage inverter for use in the embodiment asa power converter driven by PWM control. FIG. 6 is a drawing forexplaining a relation between turned-on IGBT elements and voltagevectors in eight control states of the inverter shown in FIG. 5. FIG. 7is a drawing for explaining voltage vectors. FIG. 8 is a drawing forexplaining a relation between phases and voltage vectors.

As shown in FIG. 5, the three-phase voltage inverter has a structure inwhich three sets of semiconductor switching elements, (Q1, Q4), (Q3, Q6)(Q5, Q2), that are connected to each other in series are connected inparallel to a direct-current power supply 15. Each semiconductorswitching element has incorporated therein or has mounted thereon aflywheel diode. Each semiconductor switching element may be, forexample, an IGBT element, and is hereinafter referred to as an IGBTelement. In the example shown in the drawing, the IGBT elements (Q1, Q4)are in u phase, the IGBT elements (Q3, Q6) are in v phase, and the IGBTelements (Q5, Q2) are in w phase. From the respective connection ends,three-phase voltages uvw are extracted.

Here, as for an on-off control state of the IGBT elements, each phasehas two states, in which upper-arm IGBT elements (Q1, Q3, Q5) connectedto the positive pole of the direct-current power supply 15 are turned onor lower-arm IGBT elements (Q4, Q6, Q2) connected to the negative polethereof are turned on. For three phases, 2×2×2=8 states are present.

FIG. 6 is a drawing for explaining a relation among these eight states,turned-on IGBT elements, and voltage vectors output from the three-phaseinverter. In FIG. 6, the voltage vector V0 is a vector when IGBTelements (Q4, Q6, and Q2) are turned on. The voltage vector V1 is avector when IGBT elements (Q1, Q6, and Q2) are turned on. The voltagevector V2 is a vector when IGBT elements (Q1, Q3, and Q2) are turned on.The voltage vector V3 is a vector when IGBT elements (Q4, Q3, and Q2)are turned on. The voltage vector V4 is a vector when IGBT elements (Q4,Q3, and Q5) are turned on. The voltage vector V5 is a vector when IGBTelements (Q4, Q6, and Q5) are turned on. The voltage vector V6 is avector when IGBT elements (Q1, Q6, and Q5) are turned on. The voltagevector V7 is a vector when IGBT elements (Q1, Q3, and Q5) are turned on.

A relation between each phase and each of the voltage vectors V0 to V7is as shown in FIG. 7. In FIG. 7, the voltage vectors V1 to V6 have aphase difference from one another by π/3 radian, and their magnitude isequal to the voltage Vdc of the direct-current power supply 15. Thevoltage vectors V0 and V7 are vectors each having a magnitude of 0, andare referred to as zero-voltage vectors. The phase of the voltage vectorV1 coincides with the u phase, the phase of the voltage vector V3coincides with the v phase, and the phase of the voltage vector V5coincides with the w phase.

In the three-phase voltage inverter, by varying the type of combinationof the voltage vectors V0 to V7 output during the PWM control cycle Tand their output times, voltages each having and arbitrary magnitude andphase can be output on the average. The voltage-vector control unit 11selects a type of combination of the voltage vectors V0 to V7 anddetermines the output times.

It is assumed that the voltage instructions Vu, Vv, and Vw for eachphase are given by equations (1).

$\begin{matrix}\left. \begin{matrix}{{Vu} = {{a \cdot \frac{Vdc}{\sqrt{3}} \cdot \sin}\;\theta}} \\{{Vv} = {{a \cdot \frac{Vdc}{\sqrt{3}} \cdot \sin}\;\left( {\theta - {\frac{2}{3}\pi}} \right)}} \\{\;{{Vw} = {a \cdot \frac{Vdc}{\sqrt{3}} \cdot {\sin\left( {\theta + {\frac{2}{3}\pi}} \right)}}}}\end{matrix} \right\} & (1)\end{matrix}$The phase θ in equations (1) is increased with time, but can beconsidered as being constant during the PWM control cycle T, which is ashort cycle.

Selection of the type of combination of the voltage vectors V0 to V7 isperformed as shown in FIG. 8 according to the phase θ in the current PWMcontrol cycle T. As shown in FIG. 8, the phase θ has six ranges, thatis, 0≦θ<π/3, π/3≦θ21 2π/3, 2π/3≦θ<π, π≦θ<4π/3, 4π/3≦θ<5π/3, and5π/3≦θ<2π. The number of voltage vectors to be selected is four out ofeight, but the combination of them varies for each range of the phase θ.However, the zero-voltage vectors V0 and V7 are always included in anycombination.

In FIG. 8, when the phase θ in the current PWM control cycle T is withina range of 0≦θ<π/3, for example, the combination of voltage vectors tobe selected is V1, V2, V0, and V7. Times t1, t2, t0, and t7 foroutputting these selected voltage vectors V1, V2, V0, and V7 arerespectively given by equations (2).

$\begin{matrix}\left. \begin{matrix}{t_{1} = {a \cdot T \cdot {\sin\left( {\frac{\pi}{3} - \theta} \right)}}} \\{t_{2} = {{a \cdot T \cdot \sin}\;\theta}} \\{t_{0} = {\frac{T}{2}\left( {1 - {a \cdot T \cdot {\sin\left( {\frac{\pi}{3} + \theta} \right)}}} \right)}} \\{t_{7} = {\frac{T}{2}\left( {1 - {a \cdot T \cdot {\sin\left( {\frac{\pi}{3} + \theta} \right)}}} \right)}}\end{matrix} \right\} & (2)\end{matrix}$That is, the output state of the voltage-vector control unit 11 shown inFIG. 4 represents an output state in which the phase θ in the PWMcontrol cycle T is within a range of 0≦θ<π/3, which is hereinafter usedfor description. In an area other than the area where the phase θ in thePWM control cycle T is 0≦θ<π/3, the time for outputting the selectedvoltage vector can be found in equations (2) by using, in place of θ,the remainder obtained by dividing θ by π/3.

Next, with reference to FIGS. 9 and 10A to 10C, the operation of thevoltage-vector adjusting unit 12 is described. FIG. 9 is a flowchart forexplaining the operation of the voltage-vector adjusting unit shown inFIG. 4. FIGS. 10A-10C are diagrams for explaining loci of magnetic fluxvectors when the voltage vectors are adjusted.

In FIG. 9, if the phase θ is within 0≦θ<π/3 as described above, thevoltage-vector adjusting unit 12 reads the output times t1, t2, t0, andt7 of the voltage vectors output from the voltage-vector control unit 11(step ST10), and then determines whether a total output time t0+t7 ofthe zero-voltage vectors is longer than a minimum zero-voltage-vectoroutput time Tz (step ST11).

As a result, if the total output time t0+t7 of the zero-voltage vectorsis longer than the minimum zero-voltage-vector output time Tz (stepST11: No), the read output times t1, t2, t0, and t7 are directly takenas t1′, t2′, t0′, and t7′ (step ST12).

On the other hand, if the total output time t0+t7 of the zero-voltagevectors is shorter than the minimum zero-voltage-vector output time Tz(step ST11: Yes), the output times of the voltage vectors are adjustedso that t0′+t7′=Tz. At this time, the adjusted output times t1′, t2′,t0′, and t7′ are found by equations (3) to (6), and a relative ratiobetween the output times of the voltage vectors V1 and V2 is unchanged(step ST13).t1′=(T−Tz)×t1/(t1+t2)  (3)t2′=(T−Tz)×t2/(t1+t2)  (4)t0′=Tz/2  (5)t7′=Tz/2  (6)

Then, the output times t0′, t1′, t2′, and t7′ of the voltage vectors V0,V1, V2, and V7 adjusted at either one of steps ST12 and ST13 are outputto the firing-pulse generating unit 13 (step ST14). Here, the voltagevectors V0, V1, V2, and V7 selected by the voltage-vector control unit11 are used as they are for output to the firing-pulse generating unit13.

As described above, when the voltage vectors are adjusted, a locus of amagnetic flux vector obtained through integration of the voltages can bedrawn as shown in FIGS. 10A to 10C. In FIG. 10A, a locus A of a magneticflux vector for one PWM control cycle before adjustment of the voltagevectors is depicted. In FIG. 10B, a locus A′ of the magnetic flux vectorafter adjustment of the voltage vectors is depicted. As a result ofensuring the minimum zero-voltage-vector output time for the locus A ofthe previous magnetic flux vector, the locus A′ is shorter than theprevious one. FIG. 10C is drawn by overlaying FIGS. 10A and 10B eachother.

In FIGS. 10A and 10B, magnetic flux vectors Φ0 and Φ7 are magnetic fluxvectors corresponding to the zero-voltage vectors V0 and V7. Since thezero-voltage vectors V0 and V7 do not have a magnitude, the magneticflux vectors Φ0 and Φ7 each stay at one point even with time. A magneticflux vector Φ1 is a magnetic flux vector corresponding to the voltagevector V1. The magnitude of the magnetic flux vector Φ1 is the productof the magnitude of the voltage vector V1 and its output time. Amagnetic flux vector Φ2 is a magnetic flux vector corresponding to thevoltage vector V2. The magnitude of the magnetic flux vector Φ2 is theproduct of the magnitude of the voltage vector V2 and its output time.As with the voltage vectors V1 and V2, the magnetic flux vectors Φ1 andΦ2 have a phase difference of π/3 radian.

When the voltage vectors are output in the order of V0→V1→V2→V7, thelocus A and A′ of the magnetic flux vectors are in the order ofΦ0→Φ1→Φ2→Φ7. When the load is an induction motor, the magnetic fluxvectors are equivalent to stator magnetic fluxes. Therefore, the type ofthe voltage vectors and their output times are selected so that thelocus A of the magnetic flux before the voltage-vector adjusting unit 12adjusts the voltage vectors smoothly goes along an arc. Even after thevoltage vectors are adjusted by the voltage-vector adjusting unit 12, itis required that the locus A′ of the magnetic flux smoothly goes alongthe arc.

That is, when the output times of the zero-voltage vectors V0 and V7 areincreased so that the relative ratio between the output times of thevoltage vectors V1 and V2 is unchanged, the locus A of the magnetic fluxbefore adjustment (FIG. 10A is changed to the locus A′ after adjustment(FIG. 10B. However, as shown in FIG. 10C, a triangle formed byconnecting a start point and an end point of the locus A′ together inthe PWM control cycle T is similar to a triangle formed by connecting astart point and an end point of the locus A together. Therefore, in astate where the cycle T is sufficiently short and the arc can be takenas a straight line, the end point of the locus A′ is present on the arc,as is the case of the locus A. Therefore, if the voltage vectors areadjusted with the relative ratio between the output times of the voltagevectors V1 and V2 being unchanged, the locus A′ of the magnetic fluxafter adjustment can also be made to smoothly go along the arc.

Next, with reference to FIGS. 6 and 11, the operation of thefiring-pulse generating unit 13 is described. FIG. 11 is a time chartfor explaining the operation of the firing-pulse generating unit shownin FIG. 4. The firing-pulse generating unit 13 generates on-off signalsPQ1 to PQ6 of the respective IGBT elements from the voltage vectors V1,V2, V0, and V7, which are output from the voltage-vector adjusting unit12, and the adjusted output times t1′, t2′, t0′, and t7′ of the voltagevectors. That is, the relation between the voltage vectors and the IGBTelements is shown in FIG. 6. As shown in FIG. 11, with the output timest1′, t2′, t0′, and t7′ of the voltage vectors V1, V2, V0, and V7 beingset by a time or the like, the on-off signals PQ1 to PQ6 for the IGBTelements Q1 to Q6 can be generated.

Next, with reference to FIGS. 12A and 13, description is made to aneffect of suppressing a surge voltage by keeping the output time of thezero-voltage vector at a time equal to or larger than the minimumzero-voltage-vector output time Tz. FIGS. 12A to 12D are drawings forexplaining a relation between the progression of the voltage vectors andline-to-line voltages. FIG. 13 is a drawing that depicts line-to-linevoltage patterns extracted in view of a pulse polarity, an output timeof the zero-voltage vectors, and output times of voltage vectors otherthan the zero-voltage vectors.

Here, consider the progression of the voltage vectors in two PWM controlcycles T. In consideration of only the range of the phase θ of 0≦θ<π/3due to symmetry of the vectors, the progression of the voltage vectorsis typified by the following two types shown in (1) and (2) below.

-   -   (1) V0→V1→V2→V7→V2→V1→V0    -   (2) V7→V2→V1→V0→V1→V2→V7        When the phase θ goes from the range of 0≦θ<π/3 to a range of        π/3≦θ<2π/3, the progression of the voltage vectors occurs as        typified by the following two types, which are different        from (1) and (2) above.    -   (3) V0→V1→V2→V7→V2→V3→V0    -   (4) V7→V2→V1→V0→V3→V2→V7

FIGS. 12A to 12D are drawing depicting the four types of progression ofthe voltage vectors shown in above with line-to-line voltage waveforms.It is understood from FIGS. 12A to 12D that a pulse of a line-to-linevoltage may be changed around the zero-voltage vector with the samepolarity or may be changed around the zero-voltage vector with differentpolarities. FIG. 13 is a drawing that depicts line-to-line voltagepatterns extracted from this FIGS. 12A to 12D in view of a pulsepolarity, output time of the zero-voltage vectors, and output times ofvoltage vectors other than the zero-voltage vectors. As shown FIG. 13,for combinations of long and short output times of the zero-voltagevectors and long and short output times of the voltage vectors otherthan the zero-voltage vectors, a line-to-line voltage pattern 1 may beproduced in which the voltage changes around the zero-voltage vectorwith the same polarity, and a line-to-line voltage pattern 2 may beproduced in which the voltage changes around the zero-voltage vectorwith different polarities. All line-to-line voltage changes shown inFIG. 12A to 12D are classified into the eight types shown in FIG. 13.

FIGS. 14A to 14H depicts the magnitude of each surge voltage occurringin the changes in line-to-line voltage shown in FIG. 13. As evident fromFIGS. 14A to 14H, for FIGS. 14C, 14D, 14G, and 14H where thezero-voltage-vector output time is long, no surge voltage exceedingtwice the direct-current bus voltage Vdc occurs. On the other hand, asfor FIGS 14A, 14B, 14E, and 14F where the zero-voltage-vector outputtime is short, a surge voltage exceeding twice the direct-current busvoltage Vdc occurs. It is therefore understood that appropriateselection of the output time of the zero-voltage vectors can suppressthe occurrence of a surge voltage exceeding twice the direct-current busvoltage Vdc.

As described above, in the first embodiment, when a total of two outputtimes of the zero-voltage vectors is shorter than the minimumzero-voltage-vector output time, four voltage-vector output times areadjusted so that the total of two output times of the zero-voltagevectors is equal to the minimum zero-voltage-vector output time.

Therefore, according to the first embodiment, a zero-voltage-vectoroutput time always equal to or larger than a predetermined value can beachieved. Therefore, a resonant phenomenon associated with switching ofthe IGBT elements can be attenuated while the zero-voltage vectors arebeing output, thereby effectively suppressing a surge voltage exceedingtwice the direct-current bus voltage Vdc.

Also, the adjustment of the voltage-vector output times is performed onthe output times of the voltage vectors that are parameters generatedbased on three-phase voltage instructions and are common to threephases. Therefore, with one adjustment, an effect of suppressing a surgevoltage can be obtained over all phases. Also, with the contrivance inthe adjustment of the voltage vectors, fluctuations in the locus of themagnetic flux vector associated with suppression of a surge voltage canbe minimized.

FIG. 15 is a flowchart for explaining the operation of a voltage-vectoradjusting unit included in a controlling device for the power controlleraccording to a second embodiment of the present invention. In thepower-converter control apparatus according to the second embodiment, inthe structure shown in the first embodiment (FIG. 4), some functions areadded to the voltage-vector adjusting unit 12. That is, thevoltage-vector adjusting unit 12 adjusts the output times of the voltagevectors output from the voltage-vector control unit 11 according to aprocedure shown in FIG. 15, where an adjusting operation is performedfor both of a case of ensuring the zero-voltage-vector output time to beequal to or larger than a predetermined value and a case of making thezero-voltage-vector output time zero. With reference to FIG. 15, theoperation of the voltage-vector adjusting unit 12 according to thesecond embodiment is described below. In FIG. 15, procedures identicalto those shown in FIG. 9 are provided with the same reference numerals.Here, description is made mainly to portions specific to the secondembodiment.

In FIG. 15, when the total zero-voltage-vector output time t0+t7 isshorter than the minimum zero-voltage-vector output time Tz (step ST11:No), it is further determined according to the second embodiment whetherthe total zero-voltage-vector output time t0+t7 is longer than ½ of theminimum zero-voltage-vector output time Tz (step ST20).

Then, when the total zero-voltage-vector output time t0+t7 is longerthan ½ of the minimum zero-voltage-vector output time Tz (step ST20:Yes), as with the first embodiment, the process of step ST13 isperformed. However, when the total zero-voltage-vector output time t0+t7is shorter than ½ of the minimum zero-voltage-vector output time Tz(step ST20: No), the output times of the voltage vectors are adjusted sothat t0′=t7′=0 (step ST21). Also at this time, according to equation 3,the adjustment is made so that the relative ratio between the outputtimes of the voltage vectors V1 and V2 is unchanged.

As a result, at step ST14, the output times t0′, t1′, t2′, and t7′ ofthe voltage vectors V0, V1, V2, and V7 adjusted at any one of the stepsST12, ST13, and ST21 are output to the firing-pulse generating unit 13.Here, as with the first embodiment, the voltage vectors V0, V1, V2, andV7 selected by the voltage-vector control unit 11 are used as they arefor output to the firing-pulse generating unit 13.

As described above, according to the second embodiment, when the totalzero-voltage-vector output time t0+t7 is shorter than the minimumzero-voltage-vector output time Tz, the total zero-voltage-vector outputtime is set to the minimum zero-voltage-vector output time Tz or is setto zero with t0+t7=Tz/2 being taken as a boundary. Therefore, accordingto the second embodiment, the concept of rounding-off can be applied,thereby reducing an average error of the zero-voltage-vector output timeeven with the adjustment of the voltage vectors.

Next, with reference to FIGS. 13 to 14H, suppressing a surge voltage bymaking the output time of the zero-voltage vectors zero is described. Asfor (1-1) and (1-2) in FIG. 13 and FIGS 14A and 14B, outputting a shortzero-voltage vector itself is a cause of a surge voltage exceeding twicethe direct-current bus voltage Vdc. In FIGS 14A and 14B, if nozero-voltage vector is present, one short pulse and one long pulse arepresent, which is equivalent to a waveform in a half cycle of FIGS 14Cand 14D.

Therefore, although applicable cases are limited, with the output timeof the zero-voltage vectors being made zero, the occurrence of a surgevoltage exceeding twice the direct-current bus voltage Vdc can besuppressed.

As described above, according to the second embodiment, whether toprovide a zero-voltage-vector output time equal to or larger than apredetermined value or to make the zero-voltage-vector output time zerocan be selected based on the concept of rounding-off, therebysuppressing a surge voltage exceeding twice the direct-current busvoltage Vdc. Also, the adjustment of the voltage-vector output times isperformed on the output times of the voltage vectors, which areparameters that are generated based on three-phase voltage instructionsand are common to three phases. Therefore, with one adjustment, aneffect of suppressing a surge voltage can be obtained over all phases.Furthermore, with the contrivance in the adjustment of the voltagevectors, fluctuation in the locus of the magnetic flux vector associatedwith suppression of a surge voltage can be minimized.

Also, in the above description, the boundary for determining whether thetotal zero-voltage-vector output time t0+t7 is set as the minimumzero-voltage-vector output time Tz or 0 is Tz/2. However, it goeswithout saying that the boundary is not restricted to Tz/2 and can bearbitrarily set in a range of 0 to Tz. Also, from the description of thesecond embodiment, it can be said that the first embodiment representsan example in which, with zero being taken as the boundary, the totalzero-voltage-vector output time is rounded up to the minimumzero-voltage-vector output time Tz. By contrast, it is possible to rounddown the total zero-voltage-vector output time to zero with the minimumzero-voltage-vector output time Tz being taken as the boundary.

FIG. 16 is a block diagram depicting the structure of a power-convertercontrol apparatus according to a third embodiment of the presentinvention. In the third embodiment, components are similar to those inthe first embodiment, but an exemplary structure is depicted in which,for example, two PWM control cycles are taken as a unit for control. Theconcept of the control phase θ is similar to that in the firstembodiment. Here, consider the range of 0≦θ<π/3.

In FIG. 16, with the use of the method described in the firstembodiment, a voltage-vector control unit 21 selects, from out ofvoltage instruction values Vu, Vv, and Vw of the respective phases ofthe power converter, voltage vectors to be output from the powerconverter within two control cycles of PWM control (in an example shownin the drawing, (V0_1, V1_1, V2_1, V7_1)(V0_2, V1_2, V2_2, V7_2)), andcalculates their output times (t0_1, t1_1, t2_1, t7_1)(t0_2, t1_2, t2_2,t7_2).

A voltage-vector adjusting unit 22 outputs the voltage vectors inputfrom the voltage-vector control unit 21 (in the example shown in thedrawing, (V0_1, V1_1, V2_1, V7_1)(V0_2, V1_2, V2_2, V7_2)) as they arein a method described further below (FIG. 17), and also adjusts theoutput times (t0_1, t1_1, t2_1, t7_1)(t0_2, t1_2, t2_2, t7_2) of thosevoltage vectors so that the zero-voltage-vector output time is equal toor larger than a predetermined value for output (t0_1′, t1_1′, t2_1′,t7_1′) (t0_2′, t1_2′, t2_2′, t7_2′).

With the use of the method described in the first embodiment, afiring-pulse generating unit 23 generates, based on the voltage vectorsinput from the voltage-vector adjusting unit 22 and the voltage-vectoroutput times adjusted at the voltage-vector adjusting unit 22, on-offsignals “PQ1, PQ2, PQ3, PQ4, PQ5, PQ6, and PQ7” for semiconductorswitching elements that form the power converter.

The voltage-vector control unit 21 and the firing-pulse generating unit23 perform operations of the voltage-vector control unit 11 and thefiring-pulse generating unit 13 according to the first embodiment (FIG.4) merely as being extended for two PWM control cycles, and thereforeare not described in detail. Here, with reference to FIG. 17, theoperation of the voltage-vector adjusting unit 22 is described. FIG. 17is a flowchart showing the voltage-vector adjusting unit 22 shown inFIG. 16.

In FIG. 17, when the control phase θ is in the range of f 0≦θ<π/3, thevoltage-vector adjusting unit 22 reads output times (t0_1, t1_1, t2_1,t7_1) and (t0_2, t1_2, t2_2, t7_2) of the voltage vectors output fromthe voltage-vector control unit 21 (step ST31), and then it isdetermined whether either one or both of the total zero-voltage-vectoroutput times (t0_1+t7_1) and (t0_2+t7_2) in each cycle are longer thanthe minimum zero-voltage-vector output time Tz (step ST32).

As a result, when both of the total zero-voltage-vector output times(t0_1+t7_1) and (t0_2+t7_2) in each cycle are longer than the minimumzero-voltage-vector output time Tz (step ST32: Yes), the read outputtimes t1_1, t2_1, t0_1, t7_1, t1_2, t2_2, t0_2, and t7_2 are directlytaken as adjusted output times t1_1′, t2_1′, t0_1′, t7_1′, t1_2′, t2_2′,t0_2′, and t7_2′ (step ST33).

On the other hand, when either or both of the total zero-voltage-vectoroutput times (t0_1+t7_1) and (t0_2+t7_2) in each cycle are shorter thanthe minimum zero-voltage-vector output time Tz (step ST32: No), it isdetermined whether a total of the output times of the zero-voltagevectors over two cycles (t0_1+t7_1+t0_2+t7_2) is longer than the minimumzero-voltage-vector output time Tz (step ST34).

As a result, the total of the output times of the zero-voltage vectorsover two cycles (t0_1+t7_1+t0_2+t7_2) is longer than the minimumzero-voltage-vector output time Tz (step ST34: Yes), at step ST35, theoutput time of the zero-voltage vectors between the two cycles is madezero (t7_1′=t7_2′=0), and the original amount of that output time isdistributed to the output times of the zero-voltage vectors located atboth ends of the two cycles (t0_1′=t0_2′=(t0_1+t7_1+t0_2+t7_2)/2). Here,output times of non-zero-voltage vectors other than the zero-voltagevectors are directly taken as adjusted output times of thenon-zero-voltage vectors (t1_1′=t1_1, t2_1′=t2_1, t1_2′=t1_2,t2_2′=t2_2).

On the other hand, when the total of the output times of thezero-voltage vectors over two cycles (t0_1+t7_1+t0_2+t7_2) is shorterthan the minimum zero-voltage-vector output time Tz (step ST34: No), atstep ST36, the output time of the zero-voltage vectors between the twocycles is made zero (t7_1′=t7_2′=0), and the output time of the voltagevectors are adjusted so that the output times t0_1′ and t0_2′ of thezero-voltage vectors at both ends of the two cycles become half of theminimum zero-voltage vector output time Tz (t0_1′=t0_2′=Tz/2).

At this time, according to equation 3, the adjustment is made so thatthe relative ratio of the output times of the voltage vectors V1_1,V2_1, V1_2, and V2_2 is unchanged. That is, the adjustment is made suchthat t1_1′=(T−Tz/2){t1_1/(t1_1+t2_1)}, t2_1′=(T−Tz/2){t2_1/(t1_1+t2_1)},t1_2′=(T−Tz/2){t1_2/(t1_2+t2_2)}, and t2_2′=(T−Tz/2){t2_2/(t1_2+t2_2)}.

The output times t0_1′, t1_1′, t2_1′, t7_1′, t0_2′, t1_2′, t2_2′, andt7_2′ of the voltage vectors V0_1, V1_1, V2_1, V7_1, V0_2, V1_2, V2_2,and V7_2 for two cycles adjusted at any one of steps ST33, ST35, andST36 are then output to the firing-pulse generating unit 23 (step ST37).The voltage vectors V0_1, V1_1, V2_1, V7_1, V0_2, V1_2, V2_2, and V7_2selected by the voltage-vector control unit 21 for two cycles are usedas they are for output to the firing-pulse generating unit 23.

As described above, according to the third embodiment, two PWM controlcycles are taken as a unit for adjusting the voltage vectors. With theoutput times of the zero-voltage vectors located at both ends of eachcycle being made zero, the remaining output time of the zero-voltagevectors can be doubled. Consequently, for one PWM control cycle, thetotal of the output times of the non-zero-voltage vectors does not haveto be changed until the total of the output times of the zero-voltagevectors becomes less than ½ of the minimum zero-voltage-vector outputtime Tz, thereby reducing error. According to this method, thezero-voltage-vector output time is ensured to be equal to or larger thanthe minimum zero-voltage-vector output time, or zero. Therefore, a surgevoltage exceeding twice the direct-current bus voltage Vdc can besuppressed.

Also, the adjustment of the voltage-vector output times is performed onthe output times of the voltage vectors, which are parameters that aregenerated based on three-phase voltage instructions and are common tothree phases. Therefore, with one adjustment, an effect of suppressing asurge voltage can be obtained over all phases. Furthermore, with thecontrivance in the adjustment of the voltage vectors, fluctuations inthe locus of the magnetic flux vector associated with suppression of asurge voltage can be minimized.

Also, in the third embodiment, for easy understanding, thevoltage-vector output times are adjusted for two PWM control cycles.However, the cycles for adjustment are not particularly restricted totwo cycles. It goes without saying that the cycles may be arbitrarilyset in a range of equal to or more than two cycles.

FIG. 18 is a flowchart for explaining the operation of a voltage-vectoradjusting unit included in a power-converter control apparatus accordingto a fourth embodiment of the present invention. In the power-convertercontrol apparatus according to the fourth embodiment, in the structureshown in the third embodiment (FIG. 16), some functions are added to thevoltage-vector adjusting unit 22. That is, the voltage-vector adjustingunit 22 according to the fourth embodiment adjusts the output times ofthe voltage vectors output from the voltage-vector control unit 21according to a procedure shown in FIG. 18, where, in a predeterminedcase, an adjusting operation is performed, such as collecting the outputtimes of the same voltage vectors in the two cycles as one. Withreference to FIG. 18, the operation of the voltage-vector adjusting unit22 according to the fourth embodiment is described below. In FIG. 18,procedures identical to those shown in FIG. 17 are provided with thesame reference numerals. Here, description is made mainly to portionsspecific to the fourth embodiment.

In FIG. 18, in the decision process at step ST34, when a total of outputtimes of the zero-voltage vectors over two cycles (t0_1+t7_1+t0_2+t7_2)is longer than the minimum zero-voltage-vector output time Tz (stepST34: Yes), output times of the same voltage vectors in the two cyclesare collected as one at step ST41. That is, the adjustment is made suchthat t_1′=t1_1+t1_2, t2_1′=t2_1+t2_2, andt0_1′=t7_1′=(t0_1+t7_1+t0_2+t7_2)/2. Also, the output time of eachvoltage vector in the second cycle is made zero. That is, the adjustmentis made such that t1_2′=t2_2′=t0_2′=t7_2′=0.

On the other hand, when a total of output times of the zero-voltagevectors over two cycles (t0_1+t7_1+t0_2+t7_2) is shorter than theminimum zero-voltage-vector output time Tz (step ST34: No), output timesof the same voltage vectors in the two cycles are collected as one atstep ST42. Also, the output times of the voltage vectors are adjusted sothat each of the output times t0_1′ and t7_1′ of the zero-voltagevectors after collection is half the minimum zero-voltage-vector outputtime Tz (t0_1′=t7_1′=Tz/2).

At this time, according to equation 3, the relative ratio of the outputtimes of the voltage vectors V1_1, V2_1, V1_2, and V2_2 is unchanged.That is, adjustment is made such thatt1_1′=(2T−Tz){(t1_1+t1_2)/(t1_1+t2_1+t1_2+t2_2)},t2_1′=(2T−Tz){(t2_1+t2_2)/(t1_1+t2_1+t1_2+t2_2)}. Also, the output timeof each voltage vector in the second cycle is made zero. That is,adjustment is made such that t1_2′=t2_2′=t0_2′=t7_2′=0.

Then, the output times t0_1′, t1_1′, t2_1′, t7_1′, t0_2′, t1_2′, t2_2′,and t7_2′ of voltage vectors V0_1, V1_1, V2_1, V7_1, V0_2, V1_2, V2_2,and V7_2 for two cycles adjusted at any one of steps ST33, ST41, andST42 are output to the firing-pulse generating unit 23 (step ST37).Also, the voltage vectors V0_1, V1_1, V2_1, V7_1, V0_2, V1_2, V2_2, andV7_2 selected by the voltage-vector control unit 21 for two cycles areused as they are for output to the firing-pulse generating unit 23.

As described above, according to the fourth embodiment, when the voltagevectors are adjusted by taking two PWM control cycles as a unit, outputtimes of same voltage vectors in the two control cycles are collected asone, thereby doubling the output times of the voltage vectors includingthe zero-voltage vectors. Consequently, for one PWM control cycle, thetotal of the output times of the voltage vectors other than thezero-voltage vectors does not have to be changed until the total of theoutput times of the zero-voltage vectors becomes less than ½ of theminimum zero-voltage-vector output time Tz, thereby reducing error.According to this method, the zero-voltage-vector output time is alwaysensured, and therefore a surge voltage exceeding twice thedirect-current bus voltage Vdc can be suppressed.

Also, the adjustment of the voltage-vector output times is performed onthe output times of the voltage vectors, which are parameters that aregenerated based on three-phase voltage instructions and are common tothree phases. Therefore, with one adjustment, an effect of suppressing asurge voltage can be obtained over all phases. Furthermore, with thecontrivance in the adjustment of the voltage vectors, fluctuations inthe locus of the magnetic flux vector associated with suppression of asurge voltage can also be minimized.

Also, in the fourth embodiment, for easy understanding, thevoltage-vector output times are adjusted for two PWM control cycles.However, as with the third embodiment, the cycles for adjustment are notparticularly restricted to two cycles. It goes without saying that thecycles may be arbitrarily set in a range of equal to or more than twocycles.

FIG. 19 is a block diagram showing a power-converter control apparatusaccording to a fifth embodiment of the present invention. In FIG. 19,procedures identical to those shown in FIG. 4 are provided with the samereference numerals. Here, description is made mainly to portionsspecific to the fifth embodiment.

As shown in FIG. 19, according to the fifth embodiment, in the structureshown in FIG. 4, a voltage-vector adjusting unit 31 is provided in placeof the voltage-vector adjusting unit 12, and a delay unit 32 is added.

The delay unit 32 gives the voltage vectors adjusted and output by thevoltage-vector adjusting unit 31 and their output times to thevoltage-vector adjusting unit 31 with a delay of one cycle. In anexample shown in the drawing, the delay unit 32, the delay unit 32 givesvoltage vectors V0_p, V1_p, V2_p, and V7_p with a delay of one cycle andoutput times t0_p, t1_p, t2_p, and t7_p with a delay of one cycle to thevoltage-vector adjusting unit 31.

As described in the first embodiment, the voltage-vector adjusting unit31 adjusts and outputs the output times of the voltage vectors outputfrom the voltage-vector control unit 11 so that the zero-voltage-vectoroutput time is equal to or larger than a predetermined value. At thistime, the adjusted times in one previous PWM control cycle obtainedthrough the delay unit 32 are also used for adjustment.

Next, with reference to FIG. 20, the operation of the voltage-vectoradjusting unit 31 included in the controlling device of the powerconverter according to the fifth embodiment of the present invention isdescribed. FIG. 20 is a flowchart for explaining the operation of thevoltage-vector adjusting unit 31 shown in FIG. 19. In FIG. 20,procedures identical or equivalent to the procedures shown in FIG. 9 areprovided with the same reference numerals.

In FIG. 20, the voltage-vector adjusting unit 31 reads output times t1,t2, t0, and t7 of voltage vectors input from the voltage-vector controlunit 11, voltage vectors V1_p, V2_p, V0_p, and V7_p, which are adjustedoutputs in one previous PWM control cycle that are input from the delayunit 32, and their output times t1_p, t2_p, t0_p, and t7_p (step ST51).Since the output time of the zero-voltage vectors may be zero, it isdetermined whether the vector last outputted in the previous time (inone previous PWM control cycle) is a zero-voltage vector (step ST52).

As a result, when the vector last output in the previous time is azero-voltage vector (step ST52: Yes), the procedure branches to asequence in which the process is started with the zero-voltage vector,and it is determined whether a total of output times of the zero-voltagevectors t0+t7 is longer than the minimum zero-voltage-vector output timeTz (step ST11).

When the total of output times of the zero-voltage vectors t0+t7 islonger than the minimum zero-voltage-vector output time Tz (step ST11:Yes), the output times t1, t2, t0, and t7 at the present time aredirectly taken as adjusted output times t1′, t2′, t0′, and t7′ (stepST12).

On the other hand, at step ST11, when the total of output times of thezero-voltage vectors t0+t7 is shorter than the minimumzero-voltage-vector output time Tz (step ST11: Yes), it is determinedwhether the total zero-voltage-vector output time t0+t7 is longer than ½of the minimum zero-voltage-vector output time Tz (step ST53). As aresult, when the total zero-voltage-vector output time t0+t7 is longerthan ½ of the minimum zero-voltage-vector output time Tz (step ST53:Yes), the output time t0′ of the zero-voltage vector V0 to be firstoutput in the cycle is adjusted to the total zero-voltage-vector outputtime t0+t7 (t0′=t0+t7), and the output time of the zero-voltage vectorV7 to be last output in the cycle is made zero (t7′=0). Also, the outputtimes t1 and t2 of the non-zero-voltage vectors are directly taken asadjusted times t1′ and t2′ (step ST54).

Also, in step ST53, when the total zero-voltage-vector output time t0+t7is shorter than ½ of the minimum zero-voltage-vector output time Tz(step ST53: No), at step ST55, the output time of the zero-voltagevector V0 to be first output in the cycle is adjusted to ½ of theminimum zero-voltage-vector output time Tz, and the output time of thezero-voltage vector V7 to be last output in the cycle is made zero(t7′=0). Furthermore, the output times t1 and t2 of the non-zero-voltagevectors V1 and V2 are adjusted according to equation 3 so that therelative ratio of the output times of the voltage vectors V1 and V2 isunchanged. That is, adjustment is made such thatt1′=(T−Tz/2){t1/(t1+t2)} and t2′=(T−Tz/2){t2/(t1+t2)}.

Furthermore, when the vector last output at the previous time is not azero vector (step ST52: No), the procedure branches to a sequence inwhich the procedure starts with a non-zero-voltage vector. At step ST56,when the total zero-voltage-vector output time t0+t7 is longer than ½ ofthe minimum zero-voltage-vector output time Tz step ST56: Yes), theoutput time of the zero-voltage vector V0 as the first output in thecycle is made zero (t0′=0), and the output time of the zero-voltagevector V7 as the last output in the cycle is adjusted to the totalzero-voltage-vector output time t0+t7 (t7′=t0+t7). Furthermore, as forthe output times of the non-zero-voltage vectors V1 and V2, the outputtimes t1 and t2 at this time are directly taken as adjusted output timest1′ and t2′ (step ST57).

Then, at step ST56, when the total zero-voltage-vector output time t0+t7is shorter than ½ of the minimum zero-voltage-vector output time Tz(step ST56: No), at step ST58, the output time of the zero-voltagevector V0 to be first output in the cycle is made zero (t0′=0), and theoutput time of the zero-voltage vector V7 to be last output in the cycleis adjusted to ½ of the minimum zero-voltage-vector output time Tz(t7′=Tz/2). At this time, the output times of the non-zero-voltagevectors V1 and V2 are adjusted according to equation 3 so that therelative ratio of the output times of the voltage vectors V1 and V2 isunchanged. That is, adjustment is made such thatt1′=(T−Tz/2){t1/(t1+t2)} and t2′=(T−Tz/2){t2/(t1+t2)}.

Then, the output times t0′, t1′, t2′, and t7′ of the voltage vectors V0,V1, V2, and V7 adjusted at any one of steps ST12, ST54, ST55, ST57, andST58 are output to the firing-pulse generating unit 13 (step ST14). Thevoltage vectors V0, V1, V2, and V7 selected by the voltage-vectorcontrol unit 11 are used as they are for output to the firing-pulsegenerating unit 13.

As described above, according to the fifth embodiment, the zero-voltagevectors located at the first and last of the pulse-width control cycleare combined as one, thereby doubling the output times of thezero-voltage vectors. Consequently, the total of the output times of thenon-zero-voltage vectors does not have to be changed until the total ofthe output times of the zero-voltage vectors becomes less than theminimum zero-voltage-vector output time Tz, thereby reducing error.According to this method, the zero-voltage-vector output time is ensuredto be equal to or larger than the minimum zero-voltage-vector outputtime, or is made zero. Therefore, a surge voltage exceeding twice thedirect-current bus voltage Vdc can be suppressed.

Also, the adjustment of the voltage-vector output times is performed onthe output times of the voltage vectors, which are parameters that aregenerated based on three-phase voltage instructions and are common tothree phases. Therefore, with one adjustment, an effect of suppressing asurge voltage can be obtained over all phases. Furthermore, with thecontrivance in the adjustment of the voltage vectors, fluctuations inthe locus of the magnetic flux vector associated with suppression of asurge voltage can also be minimized.

FIG. 21 is a flowchart for explaining the operation of a voltage-vectoradjusting unit included in a power-converter control apparatus accordingto a sixth embodiment of the present invention. In the power-convertercontrol apparatus according to the sixth embodiment, in the structureshown in the fifth embodiment (FIG. 19), some functions are added to thevoltage-vector adjusting unit 31. That is, the voltage-vector adjustingunit 31 according to the sixth embodiment performs an adjustingoperation by using an output time of a zero-voltage vector last outputin the previous PWM control cycle to determine an output time of azero-voltage vector to be first output in the present PWM control cycle.With reference to FIG. 21, the operation of the voltage-vector adjustingunit 31 according to the sixth embodiment is described below. In FIG.21, procedures identical to those shown in FIG. 20 are provided with thesame reference numerals. Here, description is made mainly to portionsspecific to the sixth embodiment.

In FIG. 21, upon reading output times t1, t2, t0, and t7 of voltagevectors input from the voltage-vector control unit 11, voltage vectorsV1_p, V2_p, V0_p, and V7_p, which are adjusted outputs in one previousPWM control cycle that are input from the delay unit 32, and theiroutput times t1_p, t2_p, t0_p, and t7_p (step ST51), the voltage-vectoradjusting unit 31 determines whether a total of an output time t0_p of azero-voltage vector last output at the previous time (at one previousPWM control cycle) and an output time t0 of a zero-voltage vector to befirst output at this time is longer than the minimum zero-voltage-vectoroutput time Tz (step ST61).

As a result, when the total zero-voltage-vector output time t0_p+t0 islonger than the minimum zero-voltage-vector output time Tz (step ST61:Yes), the output times t1, t2, t0, and t7 at this time are directlytaken as adjusted output times t1′, t2′, t0′, and t7′ (step ST12). Onthe other hand, when the total zero-voltage-vector output time t0_p+t0is shorter than the minimum zero-voltage-vector output time Tz (stepST61: No), it is further determined whether a total zero-voltage-vectoroutput time t0_p+t0+t7 is longer than the minimum zero-voltage-vectoroutput time Tz (step ST62).

Then, when the total zero-voltage-vector output time t0_p+t0+t7 islonger than the minimum zero-voltage-vector output time Tz (step ST62:Yes), the output time t0′ of the zero-voltage vector V0 to be firstoutput in the cycle is adjusted so that the total zero-voltage-vectoroutput time t0_p+t0 is equal to the minimum zero-voltage-vector outputtime Tz (t0′=Tz−t0_p), and the output time t7′ of the zero-voltagevector V7 to be last output in the cycle is adjusted to the remainingtime t0+t7−t0′ (t7′=t0+t7−t0′). Also, the output times t1 and t2 of thenon-zero-voltage vectors are directly taken as adjusted output times t1′and t2′ (step ST63).

On the other hand, when the total zero-voltage-vector output timet0_p+t0+t7 is shorter than the minimum zero-voltage-vector output timeTz (step ST62: No), the output time t0′ of the zero-voltage vector V0 tobe first output in the cycle is adjusted so that the totalzero-voltage-vector output time t0_p+t0 is equal to the minimumzero-voltage-vector output time Tz (t0′=Tz−t0_p), and the output timet7′ of the zero-voltage vector V7 to be last output in the cycle is madezero (t7′=0). Also, the output times t1 and t2 of the non-zero-voltagevectors are adjusted according to equation 3 so that the relative ratioof the output times of the voltage vectors V1 and V2 is unchanged. Thatis, adjustment is made such that t1′=(T−Tz+t0_p){t1/(t1+t2)} andt2′=(T−Tz+t0_p){t2/(t1+t2)} (step ST64).

Then, the output times t0′, t1′, t2′, and t7′ of the voltage vectors V0,V1, V2, and V7 adjusted at any one of steps ST12, ST63, and ST64 areoutput to the firing-pulse generating unit 13 (step ST14). The voltagevectors V0, V1, V2, and V7 selected by the voltage-vector control unit11 are used as they are for output to the firing-pulse generating unit13.

As described above, according to the sixth embodiment, with the use ofthe output time of the zero-voltage vector last output in the previousPWM control cycle, an output time of a zero-voltage vector to be outputin the present PWM control cycle is determined. Therefore, the outputtime of the zero-voltage vector can be ensured even when thezero-voltage vector extends over the PWM control cycles. Therefore, asurge voltage exceeding twice the direct-current bus voltage Vdc can besuppressed.

Also, the adjustment of the voltage-vector output times is performed onthe output times of the voltage vectors, which are parameters that aregenerated based on three-phase voltage instructions and are common tothree phases. Therefore, with one adjustment, an effect of suppressing asurge voltage can be obtained over all phases. Furthermore, with thecontrivance in the adjustment of the voltage vectors, fluctuations inthe locus of the magnetic flux vector associated with suppression of asurge voltage can also be minimized.

FIG. 22 is a block diagram depicting the structure of a power-convertercontrol apparatus according to a seventh embodiment of the presentinvention. In FIG. 22, procedures identical to those shown in FIG. 4 areprovided with the same reference numerals. Here, description is mademainly to portions specific to the seventh embodiment.

As shown in FIG. 22, according to the seventh embodiment, in thestructure shown in FIG. 4, a voltage-vector adjusting unit 41 isprovided in place of the voltage-vector adjusting unit 12, and a delayunit 42 is added.

As described in the first embodiment, the voltage-vector adjusting unit41 adjusts and outputs the output times of the voltage vectors outputfrom the voltage-vector control unit 11 so that the zero-voltage-vectoroutput time is equal to or larger than a predetermined value. In theseventh embodiment, the voltage-vector adjusting unit 41 has a functionof outputting an error Err associated with adjustment, and uses an errorErr_p input through the delay unit 42 in one previous PWM control cyclefor adjustment of the voltage vectors in one subsequent cycle.

Next, with reference to FIGS. 22 through 24C, the operation of thevoltage-vector adjusting unit 41 in the power-converter controlapparatus according to the seventh embodiment is described. FIG. 23 is aflowchart for explaining the operation of the voltage-vector adjustingunit 41 shown in FIG. 22. FIGS. 24A to 24C are drawings for explainingan error-calculating operation performed by the voltage-vector adjustingunit shown in FIG. 22.

First, in FIG. 23, the voltage-vector adjusting unit 41 reads the outputtimes t1, t2, t0, and t7 of the voltage vectors output from thevoltage-vector control unit 11 together with the error Err_p calculatedat previous time (in one previous PWM control cycle) (step ST71), andcorrects the output times t1, t2, t0, and t7 of the voltage vectors sothat the previous error Err_p is corrected (step ST72).

That is, in step ST72, the output time t1 is corrected to t1(1+Err_p).The output time t2 is corrected to t2(1+Err_p). Then, with the use ofthe new output times t1 and t2, the output times t0 and t7 are correctedto (T−t1−t2)/2. Next, with the procedure described in the secondembodiment (FIG. 15), the minimum zero-voltage-vector output time Tz isensured, or the zero-voltage-vector output time is deleted (steps ST11to ST21).

Next, an error Err is calculated between the obtained output times t1′and t2′ of the voltage vectors V1 and V2 after adjustment and the outputtimes t1 and t2 of the voltage vectors V1 and V2 corrected at step ST72.That is, Err=(t1+t2−t1′−t2′)/(t1+t2) is calculated (step ST73). Then,the obtained output times t1′, t2′, t0′, and t7′ of the voltage vectorsV1, V2, V0, and V7 after adjustment and the error Err are output (stepST74). Similarly, the voltage vectors V0, V1, V2, and V7 selected by thevoltage-vector control unit 11 are used for output to the firing-pulsegenerating unit 13.

Next, with reference to FIGS. 24A to 24C, a method of calculating theerror Err is described. In FIG. 24A, loci A and B of magnetic fluxvectors for two PWM control cycles before voltage vector adjustment areshown. The locus A is in the previous cycle, while the locus B is thecurrent cycle. In FIG. 24B, loci A′ and B′ of magnetic flux vectorsafter voltage vector adjustment are shown. As a result of ensuring theminimum zero-voltage-vector output time with the locus A of the magneticflux vectors at the previous time, it becomes the locus A′ with itslength being shortened. FIG. 24C is drawn by overlaying FIG. 24A on FIG.24B.

Here, consider the case where the end point of the locus of the magneticflux vectors before adjustment is made to agree with that afteradjustment by drawing a locus as shown in the locus B′ in the presentPWM control cycle. As has been described in the first embodiment (FIGS.10A to 10C), when the voltage vectors are adjusted according to equation3 so that the relative ratio of the output times of the voltage vectorsother than the zero-voltage vectors is unchanged, a triangle of thelocus A is similar to a triangle of the locus A′. Similarly, a triangleof the locus B is similar to a triangle of the locus B′.

When an angle Δθa and an angle Δθb are sufficiently small, the arc canbe regarded as a straight line. Therefore, the loci A and B can beconsidered as being different from the loci A′ and B′ only in dividingratio of dividing the straight line, that is, the arc, into two. Thedividing ratio between the locus A and the locus B before adjustment is1:1. When the shortened portion of the locus A′ is added to the locus B′to equalize the total values, only the ratio between the locus A and thelocus A′ is required to be known. Therefore, an error Err obtained fromany one of the following equations (7) to (9) are used.Err=(t1−t1′)/t1  (7)Err=(t2−t2′)/t2  (8)Err={t1+t2−(t1′+t2′)}/(t1+t2)  (9)

By introducing this error Err, with the use of the previous error Err_p,the output times t1 and t2 of the voltage vectors is multiplied by(1+Err_p), thereby making the end point of the magnetic flux vectors atthis time agreed with a desired point.

As such, according to the seventh embodiment, when a zero-voltage-vectoroutput time equal to or larger than a predetermined value is provided orwhen the zero-voltage-vector output time is adjusted to zero, theadjustment error can be corrected. Therefore, a surge voltage exceedingtwice the direct-current bus voltage Vdc can be reliably suppressed.Also, fluctuations in the locus of the magnetic flux vector associatedwith suppression of a surge voltage can be minimized. Furthermore, theadjustment of the voltage-vector output times is performed on the outputtimes of the voltage vectors, which are parameters that are generatedbased on three-phase voltage instructions and are common to threephases. Therefore, with one adjustment, an effect of suppressing a surgevoltage can be obtained over all phases.

FIG. 25 is a flowchart for explaining the operation of a voltage-vectoradjusting unit included in a power-converter control apparatus accordingto an eighth embodiment of the present invention. In FIG. 25, proceduresidentical or equivalent to those shown in FIG. 9 (the first embodiment)are provided with the same reference numerals. Here, description is mademainly to portions specific to the eighth embodiment.

The eighth embodiment describes an exemplary measure (steps ST81 toST85) for details (inconveniences) taken as an exception and notconsidered in the power-converter control apparatus shown in the firstembodiment (FIG. 4) when the output times of the zero-voltage vectorsare adjusted to zero as described in the second embodiment (FIG. 15).

That is, taking note of FIG. 12A, eliminating the zero-voltage vector V7does not pose the line-to-line voltages Vvw and Vwu. However, as for theline-to-line voltage Vuv, two pulses of the voltage vector V1 arepresent over the voltage vector V2. This corresponds to the case of FIG.14B, with the voltage vector V2 being replaced by the zero-voltagevector. That is, when the output time of the zero-voltage vector isadjusted to zero, depending on the non-zero-voltage-vector output time,a surge voltage may occur. In such a case, in the eighth embodiment, theconcept of ensuring the minimum zero-voltage-vector output time isapplied. Hereinafter, description is implied according to FIG. 25.

In FIG. 25, when the zero-voltage-vector output time is adjusted to zero(step ST21), it is determined whether the adjusted output time t1′ ofthe voltage vector V1 is shorter than ½ of the minimumzero-voltage-vector output time Tz (step ST81). As a result, when theadjusted output time t1′ of the voltage vector V1 is shorter than ½ ofthe minimum zero-voltage-vector output time Tz (step ST81: Yes), theoutput time t1′ is readjusted to be t1′=Tz/2. Also, the adjusted outputtime t2′ of the voltage vector V2 is readjusted to be t2′=T−Tz/2 (stepST82).

On the other hand, when the adjusted output time t1′ of the voltagevector V1 is longer than ½ of the minimum zero-voltage-vector outputtime Tz (step ST81: No), it is determined whether the adjusted outputtime t2′ of the voltage vector V2 is shorter than ½ of the minimumzero-voltage-vector output time Tz (step ST83).

As a result, when the adjusted output time t2′ of the voltage vector V2is shorter than ½ of the minimum zero-voltage-vector output time Tz(step ST83: Yes), the adjusted output time t2′ is readjusted tot2′=Tz/2. At this time, the adjusted output time t1′ of the voltagevector V1 is readjusted to t1′=T−Tz/2 (step ST84).

Then, when the adjusted output time t2′ of the voltage vector V2 islonger than ½ of the minimum zero-voltage-vector output time Tz (step83: No), the output times t1′, t2′, t0′, and t7′ adjusted at step ST11to ST21 are not readjusted (step ST85).

In the description made above, when the output time of the voltagevectors other than the zero-voltage vectors is shorter than ½ of theminimum zero-voltage-vector output time Tz, the time is rounded up toTz/2. However, as has been described in the second embodiment,rounding-off or rounding down may be performed.

As described above, according to the eighth embodiment, it is possibleto restrict a surge voltage that may occur regarding the output times ofthe voltage vectors other than the zero-voltage vectors when the outputtime of the zero-voltage vectors are adjusted to be zero. With this, asurge voltage exceeding twice the direct-current bus voltage Vdc can bereliably suppressed. Also, an effect of such suppression of a surgevoltage can be obtained over all phase only by adjusting thevoltage-vector output times, which are parameters that are common tothree phases. Furthermore, with the contrivance in the adjustment of thevoltage vectors, fluctuations in the locus of the magnetic flux vectorassociated with suppression of a surge voltage can be minimized.

FIG. 26 is a flowchart for explaining the operation of a voltage-vectoradjusting unit included in a power-converter control apparatus accordingto a ninth embodiment of the present invention. In FIG. 26, proceduresidentical or equivalent to those shown in FIG. 20 (the fifth embodiment)are provided with the same reference numerals. Here, description is mademainly to portions specific to the ninth embodiment.

The ninth embodiment describes an exemplary measure (steps ST90 to ST93)to details (inconveniences) taken as an exception and not considered inthe power-converter control apparatus shown in the fifth embodiment(FIG. 19) when the output times of the zero-voltage vectors are adjustedto zero as described in FIG. 20.

That is, when the pattern of the occurrence of a surge voltage is as inFIG. 14E and FIG. 14F, the surge voltage of the motor-end line-to-linevoltage cannot be suppressed even by elimination of the zero-voltagevector. Therefore, taking note of FIGS. 12C and 12D, in FIG. 12D, thephenomena in FIGS. 14E and 14F occur. It is evident, however, that sucha phenomenon does not occur in FIG. 12C. The progression of the voltagevectors when the phase θ makes a transition from a range of 0≦θ<π/3 to arange of π/3≦θ<2π/3 is shown below again.

-   -   (3) V0→V1→V2→V7→V2→V3→V0    -   (4) V7→V2→V1→V0→V3→V2→V7        Here, the progression becomes as follows when the zero-voltage        vectors are eliminated.    -   (3)′ V0→V1→V2→(V7)→V2→V3→V0    -   (4)′ V7→V2→V1→(V0)→V3→V2→V7        From comparison with (3)′ and (4)′, it is evident that the        phenomena in FIGS. 14E and 14F are eliminated when the voltage        vectors before and after elimination of the zero-voltage vectors        are made identical to each other, thereby suppressing a surge        voltage.

In FIG. 26, at step ST90 in place of the first step ST51 shown in FIG.20, the voltage vectors V1, V2, V0, and V7 input from the voltage-vectorcontrol unit 11, the output times t1, t2, t0, and t7, the voltagevectors V1_p, V2_p, V0_p, and V7_p, which are adjusted outputs inputfrom the delay unit 32 at one previous PWM control cycle, and theiroutput times t1_p, t2_p, t0_p, and t7_p are read. Then, when the outputtimes of the zero-voltage vectors are adjusted to zero at step ST57 orST 58, it is determined whether the voltage vector last output at theprevious time is identical to the voltage vector to be first output atthis time (step ST91).

As a result, when the voltage vector last output at the previous time isidentical to the voltage vector to be first output at the present time(step ST91: Yes), this is the case of (3)′ described above, andtherefore no process is performed and then the procedure goes to stepST93. On the other hand, when the voltage vector last output at theprevious time is different from the voltage vector to be first output atthis time (step ST91: No), this is the case of (4)′. Therefore, thevoltage vector to be first output at the present time is changed to thevector last output at the previous time (step ST92), and the proceduregoes to step ST93. At step ST93, the adjusted output times t1′, t2′,t0′, and t7′ of the voltage vectors and the voltage vectors V1′, V2′,V0′, and V7′ are output. When the procedure goes to step ST93 from anyone of steps ST12, ST54, and ST 55, the voltage vectors V0, V1, V2, andV7 selected by the voltage vector controlling unit 11 are directlyoutput as the voltage vectors V0′, V1′, V2′, and V7′ to the firing-pulsegenerating unit 13.

As such, according to the ninth embodiment, the cases of FIGS. 14E and14F occurring when the output times of the zero-voltage vectors areadjusted to zero can be avoided. Therefore, a surge voltage exceedingtwice the direct-current bus voltage Vdc can be reliably suppressed.Also, an effect of such suppression of a surge voltage can be obtainedover all phases only by adjusting the voltage-vector output times, whichare parameters that are common to three phases.

Here, in the first to ninth embodiments, separate methods forsuppressing the occurrence of a surge voltage exceeding twice thedirect-current bus voltage Vdc have been described. However, two or moreof the first to ninth embodiments can be used in combination. Thestructure in that case is not described herein. Even in combination, asurge voltage exceeding twice the direct-current bus voltage Vdc can besuppressed by at least ensuring the output time of the zero-voltagevectors equal to or larger than a predetermined value or by making theoutput time zero. Also, the adjustment of the voltage-vector outputtimes is performed on the output times of the voltage vectors, which areparameters that are generated based on three-phase voltage instructionsand are common to three phases. Therefore, with one adjustment, aneffect of suppressing a surge voltage can be obtained over all phases.Also, with the contrivance in the adjustment of the voltage vectors,fluctuations in the locus of the magnetic flux vector associated withsuppression of a surge voltage can be minimized.

Also, in the description of the first to ninth embodiments, to minimizefluctuations in the locus of the magnetic flux vector associated withsuppression, adjustment is performed so that the relative ratio of theoutput times of the voltage vectors other than the zero-voltage vectorsis unchanged. However, if suppressing a surge voltage is the onlypurpose, the relative ratio may be changed. This is evident from thedescription of the first embodiment regarding suppression of a surgevoltage.

Also in this case, a surge voltage exceeding twice the direct-currentbus voltage Vdc can be suppressed by at least ensuring the output timeof the zero-voltage vectors equal to or larger than a predeterminedvalue or by making the output time zero. Also, the adjustment of thevoltage-vector output times is performed on the output times of thevoltage vectors, which are parameters that are generated based onthree-phase voltage instructions and are common to three phases.Therefore, with one adjustment, an effect of suppressing a surge voltagecan be obtained over all phases.

INDUSTRIAL APPLICABILITY

The present invention is suitable as a power-converter control apparatuswhen a connection cable between the power converter and a load is long.

1. An apparatus for controlling a power converter in which an outputvoltage is controlled by pulse-width-modulation control, the apparatuscomprising: a voltage-vector control unit that determines, based on avoltage instruction value for the power converter, voltage vectors,including zero-voltage vectors, output from the power converter in acontrol cycle of the pulse-width-modulation control and durations ofoutputting of the voltage vectors; a voltage-vector adjusting unit thatadjusts the durations of outputting of the voltage vectors so that, iftotal of the durations of outputting of the zero-voltage vectors in thecontrol cycle is longer than a predetermined time that is longer thanzero, the voltage-vector adjusting unit adjusts durations of outputtingof the zero voltage vectors to a fixed time or longer, and, if the totalis shorter than the predetermined time, the voltage vector adjustingunit adjusts the durations of outputting of the zero voltage vectors tozero; and a firing-pulse generating unit that generates a signal forturning on and off semiconductor switching elements included in thepower converter, based on the durations of outputting of the voltagevectors, as adjusted by the voltage-vector adjusting unit.
 2. Theapparatus according to claim 1, wherein the voltage-vector adjustingunit adjusts the durations of outputting of the zero voltage vectors tothe fixed time or longer without changing relative ratio betweendurations of outputting of non-zero voltage vectors, excluding thezero-voltage vectors.
 3. The apparatus according to claim 1, wherein,the voltage-vector adjusting unit adjusts durations of outputting ofnon-zero voltage vectors, excluding the zero-voltage vectors, to anotherfixed time or longer, or to zero, if the voltage-vector adjusting unitadjusts the durations of outputting of the zero voltage vectors to zero.4. An apparatus for controlling a power converter in which an outputvoltage is controlled by pulse-width-modulation control, the apparatuscomprising: a voltage-vector control unit that determines, based on avoltage instruction value for the power converter, voltage vectors,including zero-voltage vectors, output from the power converter in aplurality of control cycles of the pulse-width-modulation control anddurations of outputting of the voltage vectors; a voltage-vectoradjusting unit that adjusts the durations of outputting of the voltagevectors so that, if total of the durations of outputting of thezero-voltage vectors in the control cycles is shorter than apredetermined time, the voltage-vector adjusting unit adjusts durationsof outputting of middle zero voltage vectors, between two adjacentcontrol cycles, to zero, and distributes the durations of outputting ofthe middle zero-voltage vectors to duration of outputting of endzero-voltage vectors at ends of the two adjacent control cycles; and afiring-pulse generating unit that generates a signal for turning on andoff semiconductor switching elements included in the power converter,based on the durations of outputting of the voltage vectors, as adjustedby the voltage-vector adjusting unit.
 5. An apparatus for controlling apower converter in which an output voltage is controlled bypulse-width-modulation control, the apparatus comprising: avoltage-vector control unit that determines, based on a voltageinstruction value for the power converter, voltage vectors, includingzero-voltage vectors, output from the power converter in a plurality ofcontrol cycles of the pulse-width-modulation control and durations ofoutputting of the voltage vectors; a voltage-vector adjusting unit thatadjusts the durations of outputting of the voltage vectors so that, iftotal of the durations of outputting of the zero-voltage vectors in thecontrol cycles is shorter than a predetermined time, the voltage-vectoradjusting unit groups durations of outputting identical voltage vectorsin the control cycles into one; and a firing-pulse generating unit thatgenerates a signal for turning on and off semiconductor switchingelements included in the power converter, based on the durations ofoutputting of the voltage vectors, as adjusted by the voltage-vectoradjusting unit.
 6. An apparatus for controlling a power converter inwhich an output voltage is controlled by pulse-width-modulation control,the apparatus comprising: a voltage-vector control unit that determines,based on a voltage instruction value for the power converter, voltagevectors, including zero-voltage vectors, output from the power converterin a control cycle of the pulse-width-modulation control and durationsof outputting of the voltage vectors; a voltage-vector adjusting unitthat adjusts the durations of outputting of the voltage vectors so that,if total of durations of outputting the zero-voltage vectors is shorterthan a predetermined value, upon receiving voltage vectors used for anadjustment in a previous control cycle, the voltage-vector adjustingunit, based on whether a voltage vector lastly output in the previouscontrol cycle is a zero-voltage vector, adjusts a first duration ofoutpuffing one of the zero-voltage vectors in a current control cycle tozero and distributes an amount of the first duration to a secondduration of outputting another of the zero-voltage vectors; and afiring-pulse generating unit that generates a signal for turning on andoff semiconductor switching elements included in the power converter,based on the durations of outputting of the voltage vectors, as adjustedby the voltage-vector adjusting unit.
 7. An apparatus for controlling apower converter in which an output voltage is controlled bypulse-width-modulation control, the apparatus comprising: avoltage-vector control unit that determines, based on a voltageinstruction value for the power converter, voltage vectors, includingzero-voltage vectors, output from the power converter in a control cycleof the pulse-width-modulation control and durations of outputting of thevoltage vectors; a voltage-vector adjusting unit that adjusts thedurations of outputting of the voltage vectors so that, upon receivingvoltage vectors used for an adjustment in a previous control cycle, if atotal of a third duration of outpuffing of a zero-voltage vector lastlyadjusted in the previous control cycle and a fourth duration ofoutputting of a zero-voltage vector firstly received from thevoltage-vector control unit in a current control cycle is shorter than apredetermined time, the voltage vector adjusting unit adjusts the fourthduration to a fifth duration which is obtained by subtracting the fourthduration from the predetermined time; a delay unit that delays thevoltage vectors output from the voltage-vector adjusting unit by onecontrol cycle, and outputs the voltage vectors to the voltage-vectoradjusting unit; and a firing-pulse generating unit that generate asignal for turning on and off semiconductor switching elements includedin the power converter, based on the durations of outputting of thevoltage vectors, as adjusted by the voltage-vector adjusting unit.
 8. Anapparatus for controlling a power converter in which an output voltageis controlled by pulse-width-modulation control, the apparatuscomprising: a voltage-vector control unit that determines, based on avoltage instruction value for the power converter, voltage vectors,including zero-voltage vectors, output from the power converter in acontrol cycle of the pulse-width-modulation control and durations ofoutputting of the voltage vectors; a voltage-vector adjusting unit thatadjusts the durations of outputting of the voltage vectors bycalculating an error generated by an adjustment of the durations ofoutputting of the voltage vectors and by correcting the durations ofoutputting of the voltage vectors in a current control cycle with theerror calculated in a previous control cycle, and adjusts total ofdurations of the zero-voltage vectors to a fixed time or longer, if thetotal is longer than a predetermined time, and adjusts the total tozero, if the total is shorter than the predetermined time; a delay unitthat delays the voltage vectors output from the voltage-vector adjustingunit by one control cycle, and outputs the voltage vectors to thevoltage-vector adjusting unit; and a firing-pulse generating unit thatgenerates a signal for turning on and off semiconductor switchingelements included in the power converter, based on the durations ofoutputting of the voltage vectors, as adjusted by the voltage-vectoradjusting unit.
 9. An apparatus for controlling a power converter inwhich an output voltage is controlled by pulse-width-modulation control,the apparatus comprising: a voltage-vector control unit that determines,based on a voltage instruction value for the power converter, voltagevectors, including zero-voltage vectors, output from the power converterin a control cycle of the pulse-width-modulation control and durationsof outputting of the voltage vectors; a voltage-vector adjusting unitthat adjusts the durations of outputting of the voltage vectors bychanging durations of outpuffing of the zero-voltage vectors to zero andreplacing a first voltage vector firstly output in a current cycle witha last voltage vector lastly output in a previous control cycle, if thelast voltage vector is different from the first voltage vector; and afiring-pulse generating unit that generates a signal for turning on andoff semiconductor switching elements included in the power converter,based on the durations of outputting of the voltage vectors, as adjustedby the voltage-vector adjusting unit.